1. Field of the Invention
The present invention relates in general to computer-aided design (CAD) tools for generating and analyzing integrated circuit (IC) layouts, and in particular to a method employed by a resistance/capacitance (RC) extraction tool for estimating resistance of signal paths described by an IC layout.
2. Description of Related Art
A typical IC die includes a semiconductor substrate containing transistors and other objects and conductors formed on layers of insulating material above the substrate for routing signals between the transistors and other objects in the substrate. Designers often want to know the path delays through signal paths formed by these conductors, and since the path delay through a conductor is largely a function of its shunt capacitance and series resistance, designers employ RC extraction tools to determine the resistances and capacitances of the conductors forming those signal paths. The resistance of any conductor is a function of its length and cross-sectional area and of the resistivity of the material forming it. An RC extraction tool processes layout data describing the IC layout to determine the dimensions of each conductor on each layer so that it can calculate its resistance.
The conductor and other IC component dimensions indicated by the layout data control the dimensions and positions of apertures in a set of photo-lithographic masks employed during IC fabrication, and these apertures and the spacing between them in turn control the actual dimensions of and spacing between the conductors and other objects of the IC.
FIG. 1 is a sectional elevation view of an upper portion of an IC during the fabrication process including a metal layer 10 formed on an insulating layer 11. A layer 13 of photoresist material has been deposited on metal layer 10. Apertures 15 between areas 17 of a photo-lithographic mask 14 permit light 16 to strike photoresist layer 13 above areas of metal layer 10 that are to be removed. Light 16 sensitizes those areas of photoresist material 13 so that they, and the portions of metal layer 10 below them, can be etched away.
FIG. 2 illustrates a set of conductors 18A–18D formed from metal layer 10 after it has been etched and residual portions of photoresist material 13 have been removed. Note that conductors 18A–18D are slightly narrower than the portions 17 of mask 14 of FIG. 1 that defined them due to effects of light diffraction at the edges of apertures 15. An RC extraction tool processing the layout data defining mask 14 that assumes conductors 18A–18D will be of the same width and the dimensions of the areas 17 of mask 14 directly above them will underestimate the resistance of conductor's 18A–18D because it will overestimate their widths. However the percentage of resistance underestimation will be small when mask areas 17 and the apertures 15 between them are relatively wide because diffusion effects will narrow conductors 18A–18D only by a small percentage of their widths.
As transistors and other IC components have grown steadily smaller over the years, so too have conductor widths and the minimum spacing between adjacent conductors on the same layer. FIG. 3 is a sectional elevation view of an upper portion of an IC during the fabrication process including a metal layer 19 formed on an insulating layer 20. A layer 26 of photoresist material has been deposited on metal layer 19. Apertures 22 in a photo-lithographic mask 21 permit light 23 to strike photoresist layer 26 above areas of metal layer 19 that are to be removed while mask areas 24 block light from reaching areas of metal layer 19 that are to remain. FIG. 4 illustrates a resulting set of conductors 25A–25D formed from metal layer 10 after it has been etched and residual portions of photoresist material 13 have been removed.
In the example of FIGS. 3 and 4, the relatively narrow mask aperture 22 diffuse light farther beyond their edges than the relatively wide apertures of FIG. 1. Thus conductors 25A–25D of FIG. 4 are substantially narrower than conductors 18A–18D of FIG. 2 even though the mask areas 24 defining conductors 25A–25D and mask areas 17 defining conductors 18A–18D are of the same width. Note the lack of uniformity of width of conductors 25A–25D. Conductors 25B and 25C are substantially narrower than conductors 25A and 25D because apertures 22 produced substantial diffusion-related conductor narrowing on both sides of conductors 25B and 25C and on only one side of each of conductors 25A and 25D. Thus an RC extraction tool processing layout data defining mask 21 would overestimate the widths of conductors 25A and 25D by a substantial amount and would overestimate the widths of conductors 25B and 25C by an even greater amount. The overestimation of conductor width results in an underestimation of conductor resistance, and that can lead to substantial errors in estimation of path delays through the conductors.
FIG. 5 is a plan view of several conductors 30–37 formed on an IC layer along a set of evenly spaced grid lines G=1 through 6. The areas of the photo-lithographic mask used to define conductors 30–37 were of similar widths, but in this example grid lines 1–6 are sufficiently close together that diffusion effects substantially narrow adjacent conductors. Note for example, that conductor 32 is narrowed on its left side in areas proximate to conductors 30 and 31 and is narrowed on its right side in areas proximate to conductors 33 and 34.
An RC extraction tool estimating the actual dimensions of any of conductors 30–37 based on the information contained in IC layout data must therefore take into account not only the nominal dimensions that conductor would have in the absence of diffusion effects, but must also take into account the nominal dimensions and relative position of adjacent conductors so that it can adjust its estimates of conductor dimensions to account for diffusion effects.
Layout data typically indicates positions of endpoints of each conductor of each layer along the layer's grid lines. To determine the resistance of, for example, conductor 32 of FIG. 5 merely from positions of that conductor's endpoints along grid line 2 as indicated by the IC layout data, an RC extraction tool must also know not only the nominal width of the conductor, but also the positions and dimensions of endpoints of its neighboring conductors 30, 31, 33 and 34 so that it can take into account diffraction effect with ascertaining the actual shape of conductor 32. Thus after determining the position and nominal dimensions conductor 32 from the layout data, an RC extraction must search the layout data to determine whether any other conductors are sufficiently close to conductor 32 to cause diffraction-related effects on the shape of conductor 32. This need to search the layout data to find each conductor's neighbors can substantially increase the number of times an RC extraction tool must access the layout data for each conductor, thereby substantially increasing the amount of time it needs to estimate conductor resistance, particularly when the RC extraction tool does not have sufficient memory resources to hold all of the layout data in memory at the same time.
What is needed is a method for processing layout data to estimate conductor resistances that minimizes the number of times data describing the position and nominal dimensions of each conductor is accessed.